Introduction:
The Floating-Point Unit (FPU) provides high-performance floating-point processing capabilities for use in graphics processing, scientific, engineering, and business applications.
The FPU represents a separate execution environment within the IA-32 architecture. This execution environment consists of 8 data registers and following special purpose registers.
- The status register
- The counter register
- The tag word register
Mechanism:
The FPU data register consists of eight 80-bits registers. Values are stored in these register in the double extended-precision floating point format. When floating-point, integer, or packed BCD integer values are loaded from memory into any of the FPU data registers, the values are automatically converted into the double extended-precision floating-point format (if they are not already in that format). When computation results are subsequently transferred back into memory from any of the FPU registers, the results can be left in the double extended-precision floating-point format or converted back into a shorter floating-point format, an integer format, or the packed BCD integer format.
The FPU instructions treat the eight FPU data register as a register stack.All addressing of the data registers is relative to the register on the top of the stack.
The register number of the current top-of-stack register is stored in the TOP (stack TOP) field in the FPU status word. Load operations decrement TOP by one and load a value into the new top-of-stack register, and store operations store the value from the current TOP register in memory and then increment TOP by one. (For the FPU, a load operation is equivalent to a push and a store operation is equivalent to a pop.) Note that load and store operations are also available that do not push and pop the stack.